By Jörg Henkel, Sri Parameswaran
To the hard-pressed platforms clothier this ebook will come as a godsend. it's a hands-on consultant to the numerous ways that processor-based platforms are designed to permit low energy units. protecting a major diversity of themes, and co-authored by way of the various field’s most sensible practitioners, the e-book presents an exceptional place to begin for engineers within the sector, and to investigate scholars embarking upon paintings on embedded platforms and architectures.
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Additional resources for Designing Embedded Processors: A Low Power Perspective
For example, it can be an IP, reused from other designs, generated by HLS, or specified by the designer. The datapath description is captured in a Generic Netlist Representation (GNR). A component in datapath can be a register, register file, bus, multiplexer, functional unit, memory, etc. The program, written in a high-level language such as C, is first compiled and optimized by a front-end and then mapped (scheduled and bound) on the given datapath. The compiler generates the stream of control values as well as the contents of data memory.
Various methods to 18 J¨org Henkel et al. , 2003). Parameterizations in the extensible processor platform leads to the setting of the register file size, instruction and data cache sizes, and memory configuration. Jain et al. (2001) proposed a method to evaluate the register file size. , 1998; Wolf and Kandemir, 2003). Finally, Abraham and Rau (2000) described a scheme to select instruction and data cache size. They and Lee et al. (2002) presented examples of design exploration with multiple architectural customizations under a single constraint.
In order to enable the local memory access, memory accesses need to be carefully scheduled, or multiple read/write ports are needed. In addition, accessing memory elements in the execution stage potentially increases pipeline hazards, thus increasing the complexity of code optimization. This approach increases the performance of the application at a certain hardware overhead. Clark et al. (2003) described a compiler approach to generate instructions in VLIW architecture without constraining their size or shape.